Intel has unveiled a refreshed process roadmap extending through 2025 and beyond, moving away from simple node naming toward a more transparent mix of technologies, packaging, and specialized IP. The updated plan highlights how the company intends to blend next-generation silicon, advanced packaging, and unique accelerators to compete across data center, client, and edge workloads.
As part of this shift, Intel is emphasizing clearer performance-per-watt targets, expanded foundry options, and closer alignment with software ecosystems, signaling a more collaborative approach to semiconductor manufacturing and design.
| Process Node | Key Transistor Technology | Target Segment | Expected Ramp |
|---|---|---|---|
| Intel 18A | Gate-All-Around nanosheet | High-performance client & data center | 2024 risk production, 2025 high-volume |
| Intel 20A | Gate-All-Around nanosheet with RibbonFET | Client mobile & mainstream compute | 2024 production start |
| Intel 22A | Enhanced 22FFL with PowerVia | IoT, edge, and specialized accelerators | 2024 development phase |
| Specialized Tiles | EMIB, Foveros, MCM packaging | Multi-die systems and custom silicon | 2023 onward in production |
Intel Gate-All-Around Nanosheet Transistors Through 2025
Intel is advancing its version of gate-all-around transistors, previously called RibbonFET, positioning it as the core of Intel 20A and Intel 18A nodes. This architecture delivers better electrostatic control, higher drive current, and reduced leakage compared to previous FinFET designs.
By stacking nanosheets horizontally and optimizing channel width, Intel aims to sustain scaling benefits while improving yield and manufacturability. The transition is being staged across two process generations to balance risk and performance.
PowerVia Backside Power Delivery Integration
Intel’s PowerVia technology moves critical power delivery layers behind the active transistor layer, freeing up the front side for routing and improving signal integrity. This approach is slated for introduction at the Intel 20A node and matures at Intel 18A, enabling higher frequencies and more compact dies.
The combination of nanosheet transistors and backside power delivery is designed to lower voltage, reduce power consumption, and unlock new form factors, particularly in client and edge applications where power and thermal constraints are stringent.
Memory Interconnect Innovation and Packaging Roadmap
Intel is expanding its packaging roadmap to include more advanced embedded memory options, multi-die integration, and chiplet-style designs that connect specialized tiles via EMIB and Foveros. These technologies allow the company to mix process nodes and optimize cost, performance, and area for each component.
Enhanced memory channels, both within packages and across multi-chip modules, will target bandwidth-intensive workloads such as AI inferencing, networking, and high-throughput computing, broadening the applicability of Intel’s process strategy.
Data Center, Client, and Edge Workload Alignment
The refreshed roadmap aligns process introductions with specific workload requirements, ensuring that nodes like Intel 20A focus on mobile efficiency, while Intel 18A targets demanding data center and high-performance computing applications. This segmentation enables more tailored transistor configurations, IO densities, and thermal profiles.
By coordinating process launches with software optimizations and ecosystem partnerships, Intel aims to reduce time-to-market for new architectures and accelerate adoption across servers, clients, and intelligent edge devices.
Accelerated Innovation Across Data Center, Client, and Edge Segments
Intel’s process roadmap through 2025 reflects a broader strategy to compete across diverse segments by aligning transistor innovation, packaging, and memory architectures with real-world workload requirements. This coordinated approach is intended to strengthen the company’s position in high-growth markets while maintaining leadership in established segments.
- Prioritize Gate-All-Around nanosheet transistors at Intel 20A and Intel 18A for scalable performance
- Integrate PowerVia backside power delivery to reduce losses and enable denser designs
- Leverage EMIB and Foveros packaging for multi-die systems and specialized accelerators
- Align process introductions with memory and IO requirements of data center and edge workloads
- Optimize yield and cost through segmentation and staged risk production
FAQ
Reader questions
How will Intel balance advanced nodes with cost and yield challenges through 2025?
Intel plans a staged rollout where risk production begins at Intel 18A in 2024, followed by high-volume manufacturing at Intel 20A and Intel 18A in 2025, using specialized tiles and multi-die designs to manage yield and cost across segments.
What role do specialized tiles and packaging play in Intel’s updated roadmap through 20EMBED
Specialized tiles combined with EMIB and Foveros packaging allow Intel to integrate IP built on different processes, enabling faster innovation, better yields, and more flexible product configurations for data center, client, and edge markets.
How do PowerVia and nanosheet transistors together improve performance-per-watt for client and edge devices?
PowerVia reduces resistive losses on the backside of the die, while nanosheet transistors improve switching efficiency, together enabling higher clocks at lower voltage and significantly better performance-per-watt for mobile and edge form factors.
Which workloads will directly benefit from the updated Intel process roadmap targeting 2025?
Workloads such as AI inferencing, high-throughput networking, real-time analytics, and power-constrained client computing will directly benefit from the increased transistor density, improved interconnects, and specialized accelerators outlined in the roadmap.