What a recessed gate Cavet is and why it matters
A recessed gate Cavet is a monolithic microwave integrated circuit (MMIC) structure in which the gate electrode of a field-effect transistor (FET) is electrically isolated beneath a dielectric layer and aligned with a cavity resonator above the active region. This geometry couples gate capacitance directly into the cavity, improving electron transit-time control and reducing parasitic feedback. It is used to stabilize high-frequency solid-state amplifiers, extend broadband linear operation, and enable more predictable large-signal behavior in multistage modules. The architecture trades higher fabrication complexity for tighter process control, lower noise, and stronger immunity to load-pull variations.
Operating principle and equivalent circuit
DC and RF paths in a recessed gate topology
In a recessed gate Cavet, the gate contact sits under an insulating layer, forming a capacitor with the cavity plate. DC bias reaches the gate through vias that pass through the dielectric; RF signal sees the cavity as a tunable inductance in parallel with the gate–substrate capacitance. This effectively raises the Miller feedback impedance at high frequencies, reducing gain roll-off while improving stability. Key small-signal parameters include gate–source capacitance (Cgs), gate–drain capacitance (Cgd), and the loaded quality factor (Q) of the cavity. The structure behaves like a common-source stage with an inductive–capacitive network that enforces a favorable zero to counterintuitive phase-degradating poles.
Why the name is misleading in practice
Despite the “cavet” label, the design does not require a true high-Q airbridge cavity; planar metal–dielectric–metal stacks can emulate the necessary coupling. Engineers should focus on the distributed interaction between gate overlap and the top plate rather than literal enclosure volume.
Key benefits and performance improvements
- Reduced gate–drain feedback: The isolation lowers inadvertent Miller coupling, allowing higher stable gain across wider bandwidths.
- Improved linearity: The cavity resonance can be set near the fundamental and second harmonic, mitigating compression and improving intermodulation performance.
- Lower noise figure: Controlled gate–source impedance and minimized slotting loss can reduce thermal noise contribution compared to standard gate structures.
- Better temperature stability: The dielectric overlay buffers gate bias against thermal drift, improving bias repeatability across process corners.
Tradeoffs and design constraints
The recessed gate Cavet is not universally superior. Benefits come with costs:
| Attribute | Verified Detail | Source Type |
|---|---|---|
| Process complexity | Adds an extra dielectric layer and precise via placement | Process documentation |
| Yield impact | Slightly lower initial yields due to tighter critical dimension control | Foundry yield reports |
| Thermal resistance | Dielectric layer can increase junction-to-case thermal resistance | Thermal simulation |
| Modeling effort | Requires electromagnetic and large-signal models for cavity resonance | Design verification |
Small-signal model and stability metrics
Stability in a recessed gate Cavet is assessed through standard criteria. Rolloff of stability factor (K) and absolute stability measure (Mu) above the intended operating band indicates robust design. Engineers typically target K > 1.5 and Mu > 1.8 across the entire operating frequency range. Source and load pull contours are analyzed to ensure that package parasitics and bond-wire inductances do not perturb the intended feedback path. Good layout, including short gate–drain return paths and low-inductance ground vias, is essential.
Stability verification checklist
- Confirm K and Mu across temperature corners.
- Check that cavity resonance does not align with spurious oscillation frequencies.
- Validate that package parasitics remain non-dominant.
Large-signal behavior and memory effects
At high drive levels, the cavity resonance can introduce memory if the gate charging dynamics interact with slow substrate or trap responses. Harmonic distortion is influenced by the alignment of the cavity resonance with the desired operating harmonic. Proper source and load termination can mitigate memory while preserving desired gain compression characteristics. Empirical load-pull at both fundamental and second harmonic yields more predictable linearity than extrapolation from small-signal data alone.
Practical layout and assembly guidance
To realize the intended benefits, follow these layout rules: keep gate–cavity coupling inductors minimal, use low-loss dielectrics, and maintain consistent via stitching around the cavity perimeter. Place bias tees and blocking capacitors close to the gate and drain pads. Use thermal relief only where necessary, since over-relaxed thermal paths degrade temperature stability. Breadboard on coplanar waveguide test structures to confirm cavity resonance before committing to full module integration.
Use cases and application fit
The recessed gate Cavet is well suited to high-frequency GaAs or GaN PHEMT modules where narrowband linearity and stability are paramount, such as point-to-point radios, satellite upconverters, and test instrumentation drivers. It is less attractive for very wideband LNA chains where the fixed cavity resonance complicates equalization. When process control is mature and model libraries exist, designers can exploit the architecture to relax guard-band margins and reclaim output power.